SNES Hardware Register Definitions. More...

#include <snes/types.h>

Macros
#define	BGMODE_MODE0 0

#define	BGMODE_MODE1 1

#define	BGMODE_MODE2 2

#define	BGMODE_MODE3 3

#define	BGMODE_MODE7 7

#define	INIDISP_BRIGHTNESS(n) ((n) & 0x0F)

#define	INIDISP_FORCE_BLANK 0x80

#define	NMITIMEN_JOY_ENABLE 0x01

#define	NMITIMEN_NMI_ENABLE 0x80

#define	REG_A1B(n) ((vu8)(0x4304 + ((n) << 4)))
	DMA A-bus bank for channel n.

#define	REG_A1TH(n) ((vu8)(0x4303 + ((n) << 4)))
	DMA A-bus address high for channel n.

#define	REG_A1TL(n) ((vu8)(0x4302 + ((n) << 4)))
	DMA A-bus address low for channel n.

#define	REG_APUIO0 ((vu8)0x2140)
	APU I/O port 0 (R/W)

#define	REG_APUIO1 ((vu8)0x2141)
	APU I/O port 1 (R/W)

#define	REG_APUIO2 ((vu8)0x2142)
	APU I/O port 2 (R/W)

#define	REG_APUIO3 ((vu8)0x2143)
	APU I/O port 3 (R/W)

#define	REG_BBAD(n) ((vu8)(0x4301 + ((n) << 4)))
	DMA B-bus address for channel n.

#define	REG_BG12NBA ((vu8)0x210B)
	BG1/2 tile data address (W)

#define	REG_BG1HOFS ((vu8)0x210D)
	BG1 horizontal scroll (W, 2x write)

#define	REG_BG1SC ((vu8)0x2107)
	BG1 tilemap address (W)

#define	REG_BG1VOFS ((vu8)0x210E)
	BG1 vertical scroll (W, 2x write)

#define	REG_BG2HOFS ((vu8)0x210F)
	BG2 horizontal scroll (W, 2x write)

#define	REG_BG2SC ((vu8)0x2108)
	BG2 tilemap address (W)

#define	REG_BG2VOFS ((vu8)0x2110)
	BG2 vertical scroll (W, 2x write)

#define	REG_BG34NBA ((vu8)0x210C)
	BG3/4 tile data address (W)

#define	REG_BG3HOFS ((vu8)0x2111)
	BG3 horizontal scroll (W, 2x write)

#define	REG_BG3SC ((vu8)0x2109)
	BG3 tilemap address (W)

#define	REG_BG3VOFS ((vu8)0x2112)
	BG3 vertical scroll (W, 2x write)

#define	REG_BG4HOFS ((vu8)0x2113)
	BG4 horizontal scroll (W, 2x write)

#define	REG_BG4SC ((vu8)0x210A)
	BG4 tilemap address (W)

#define	REG_BG4VOFS ((vu8)0x2114)
	BG4 vertical scroll (W, 2x write)

#define	REG_BGMODE ((vu8)0x2105)
	BG mode and tile size (W)

#define	REG_CGADD ((vu8)0x2121)
	CGRAM address (W)

#define	REG_CGADSUB ((vu8)0x2131)
	Color math control B (W)

#define	REG_CGDATA ((vu8)0x2122)
	CGRAM data write (W)

#define	REG_CGWSEL ((vu8)0x2130)
	Color math control A (W)

#define	REG_COLDATA ((vu8)0x2132)
	Fixed color data (W)

#define	REG_DASH(n) ((vu8)(0x4306 + ((n) << 4)))
	DMA size high for channel n.

#define	REG_DASL(n) ((vu8)(0x4305 + ((n) << 4)))
	DMA size low for channel n.

#define	REG_DMAP(n) ((vu8)(0x4300 + ((n) << 4)))
	DMA parameters for channel n.

#define	REG_HDMAEN ((vu8)0x420C)
	HDMA enable (W)

#define	REG_HTIMEH ((vu8)0x4208)
	H-count timer high (W)

#define	REG_HTIMEL ((vu8)0x4207)
	H-count timer low (W)

#define	REG_HVBJOY ((vu8)0x4212)
	H/V blank and joypad status (R)

#define	REG_INIDISP ((vu8)0x2100)
	Display control (W)

#define	REG_JOY1H ((vu8)0x4219)
	Joypad 1 data high (R)

#define	REG_JOY1L ((vu8)0x4218)
	Joypad 1 data low (R)

#define	REG_JOY2H ((vu8)0x421B)
	Joypad 2 data high (R)

#define	REG_JOY2L ((vu8)0x421A)
	Joypad 2 data low (R)

#define	REG_JOY3H ((vu8)0x421D)
	Joypad 3 data high (R)

#define	REG_JOY3L ((vu8)0x421C)
	Joypad 3 data low (R)

#define	REG_JOY4H ((vu8)0x421F)
	Joypad 4 data high (R)

#define	REG_JOY4L ((vu8)0x421E)
	Joypad 4 data low (R)

#define	REG_JOYA ((vu8)0x4016)
	Joypad Port A data/strobe (R/W: read serial data, write bit 0 to latch)

#define	REG_JOYB ((vu8)0x4017)
	Joypad Port B data (R: read serial data for port 2)

#define	REG_M7A ((vu8)0x211B)
	Mode 7 matrix A (W, 2x write: low then high)

#define	REG_M7B ((vu8)0x211C)
	Mode 7 matrix B (W, 2x write: low then high)

#define	REG_M7C ((vu8)0x211D)
	Mode 7 matrix C (W, 2x write: low then high)

#define	REG_M7D ((vu8)0x211E)
	Mode 7 matrix D (W, 2x write: low then high)

#define	REG_M7SEL ((vu8)0x211A)
	Mode 7 settings (W)

#define	REG_M7X ((vu8)0x211F)
	Mode 7 center X (W, 2x write: low then high)

#define	REG_M7Y ((vu8)0x2120)
	Mode 7 center Y (W, 2x write: low then high)

#define	REG_MDMAEN ((vu8)0x420B)
	DMA enable (W)

#define	REG_MEMSEL ((vu8)0x420D)
	FastROM enable (W)

#define	REG_MOSAIC ((vu8)0x2106)
	Mosaic effect (W)

#define	REG_MPYH ((vu8)0x2136)
	Multiplication result high (R)

#define	REG_MPYL ((vu8)0x2134)
	Multiplication result low (R)

#define	REG_MPYM ((vu8)0x2135)
	Multiplication result mid (R)

#define	REG_NMITIMEN ((vu8)0x4200)
	Interrupt enable (W)

#define	REG_OAMADDH ((vu8)0x2103)
	OAM address high (W)

#define	REG_OAMADDL ((vu8)0x2102)
	OAM address low (W)

#define	REG_OAMDATA ((vu8)0x2104)
	OAM data write (W)

#define	REG_OAMDATAREAD ((vu8)0x2138)
	OAM data read (R)

#define	REG_OBJSEL ((vu8)0x2101)
	Object (sprite) size and base (W)

#define	REG_OPHCT ((vu8)0x213C)
	H counter latch (R)

#define	REG_OPVCT ((vu8)0x213D)
	V counter latch (R)

#define	REG_RDCGRAM ((vu8)0x213B)
	CGRAM data read (R)

#define	REG_RDDIVH ((vu8)0x4215)
	Division result high (R)

#define	REG_RDDIVL ((vu8)0x4214)
	Division result low (R)

#define	REG_RDIO ((vu8)0x4213)
	I/O port read (R)

#define	REG_RDMPYH ((vu8)0x4217)
	Multiplication result high (R)

#define	REG_RDMPYL ((vu8)0x4216)
	Multiplication result low (R)

#define	REG_RDNMI ((vu8)0x4210)
	NMI flag and version (R)

#define	REG_RDVRAMH ((vu8)0x213A)
	VRAM data read high (R)

#define	REG_RDVRAML ((vu8)0x2139)
	VRAM data read low (R)

#define	REG_SETINI ((vu8)0x2133)
	Screen mode/video select (W)

#define	REG_SLHV ((vu8)0x2137)
	Software latch H/V counter (R)

#define	REG_STAT77 ((vu8)0x213E)
	PPU status flags (R)

#define	REG_STAT78 ((vu8)0x213F)
	PPU status flags 2 (R)

#define	REG_TIMEUP ((vu8)0x4211)
	IRQ flag (R)

#define	REG_TM ((vu8)0x212C)
	Main screen designation (W)

#define	REG_TMW ((vu8)0x212E)
	Main screen window mask (W)

#define	REG_TS ((vu8)0x212D)
	Sub screen designation (W)

#define	REG_TSW ((vu8)0x212F)
	Sub screen window mask (W)

#define	REG_VMADDH ((vu8)0x2117)
	VRAM address high (W)

#define	REG_VMADDL ((vu8)0x2116)
	VRAM address low (W)

#define	REG_VMAIN ((vu8)0x2115)
	VRAM address increment mode (W)

#define	REG_VMDATAH ((vu8)0x2119)
	VRAM data write high (W)

#define	REG_VMDATAL ((vu8)0x2118)
	VRAM data write low (W)

#define	REG_VTIMEH ((vu8)0x420A)
	V-count timer high (W)

#define	REG_VTIMEL ((vu8)0x4209)
	V-count timer low (W)

#define	REG_W12SEL ((vu8)0x2123)
	BG1/BG2 window mask settings (W)

#define	REG_W34SEL ((vu8)0x2124)
	BG3/BG4 window mask settings (W)

#define	REG_WBGLOG ((vu8)0x212A)
	BG1-4 window logic (W)

#define	REG_WH0 ((vu8)0x2126)
	Window 1 left position (W)

#define	REG_WH1 ((vu8)0x2127)
	Window 1 right position (W)

#define	REG_WH2 ((vu8)0x2128)
	Window 2 left position (W)

#define	REG_WH3 ((vu8)0x2129)
	Window 2 right position (W)

#define	REG_WOBJLOG ((vu8)0x212B)
	OBJ/MATH window logic (W)

#define	REG_WOBJSEL ((vu8)0x2125)
	OBJ/MATH window mask settings (W)

#define	REG_WRDIVB ((vu8)0x4206)
	Divisor (W)

#define	REG_WRDIVH ((vu8)0x4205)
	Dividend high (W)

#define	REG_WRDIVL ((vu8)0x4204)
	Dividend low (W)

#define	REG_WRIO ((vu8)0x4201)
	I/O port write (W)

#define	REG_WRMPYA ((vu8)0x4202)
	Multiplicand A (W)

#define	REG_WRMPYB ((vu8)0x4203)
	Multiplicand B (W)

#define	TM_BG1 BIT(0)

#define	TM_BG2 BIT(1)

#define	TM_BG3 BIT(2)

#define	TM_BG4 BIT(3)

#define	TM_OBJ BIT(4)

Detailed Description

SNES Hardware Register Definitions.

Memory-mapped I/O register addresses for PPU, CPU, DMA, and other SNES hardware components.

Usage

// Write to PPU register
REG_INIDISP = 0x80;  // Force blank
 
// Read from CPU register
u8 status = REG_RDNMI;

Reference

See docs/hardware/MEMORY_MAP.md for complete register documentation.

Author: OpenSNES Team

Copyright: MIT License

Attribution

Register definitions based on:

SNESdev Wiki (https://snes.nesdev.org/)
Fullsnes by Nocash
PVSnesLib by Alekmaul

Macros

Detailed Description

Usage

Reference

Attribution