Picture Processing Unit registers. More...

Macros
#define	REG_BG12NBA ((vu8)0x210B)
	BG1/2 tile data address (W)

#define	REG_BG1HOFS ((vu8)0x210D)
	BG1 horizontal scroll (W, 2x write)

#define	REG_BG1SC ((vu8)0x2107)
	BG1 tilemap address (W)

#define	REG_BG1VOFS ((vu8)0x210E)
	BG1 vertical scroll (W, 2x write)

#define	REG_BG2HOFS ((vu8)0x210F)
	BG2 horizontal scroll (W, 2x write)

#define	REG_BG2SC ((vu8)0x2108)
	BG2 tilemap address (W)

#define	REG_BG2VOFS ((vu8)0x2110)
	BG2 vertical scroll (W, 2x write)

#define	REG_BG34NBA ((vu8)0x210C)
	BG3/4 tile data address (W)

#define	REG_BG3HOFS ((vu8)0x2111)
	BG3 horizontal scroll (W, 2x write)

#define	REG_BG3SC ((vu8)0x2109)
	BG3 tilemap address (W)

#define	REG_BG3VOFS ((vu8)0x2112)
	BG3 vertical scroll (W, 2x write)

#define	REG_BG4HOFS ((vu8)0x2113)
	BG4 horizontal scroll (W, 2x write)

#define	REG_BG4SC ((vu8)0x210A)
	BG4 tilemap address (W)

#define	REG_BG4VOFS ((vu8)0x2114)
	BG4 vertical scroll (W, 2x write)

#define	REG_BGMODE ((vu8)0x2105)
	BG mode and tile size (W)

#define	REG_CGADD ((vu8)0x2121)
	CGRAM address (W)

#define	REG_CGADSUB ((vu8)0x2131)
	Color math control B (W)

#define	REG_CGDATA ((vu8)0x2122)
	CGRAM data write (W)

#define	REG_CGWSEL ((vu8)0x2130)
	Color math control A (W)

#define	REG_COLDATA ((vu8)0x2132)
	Fixed color data (W)

#define	REG_INIDISP ((vu8)0x2100)
	Display control (W)

#define	REG_M7A ((vu8)0x211B)
	Mode 7 matrix A (W, 2x write: low then high)

#define	REG_M7B ((vu8)0x211C)
	Mode 7 matrix B (W, 2x write: low then high)

#define	REG_M7C ((vu8)0x211D)
	Mode 7 matrix C (W, 2x write: low then high)

#define	REG_M7D ((vu8)0x211E)
	Mode 7 matrix D (W, 2x write: low then high)

#define	REG_M7SEL ((vu8)0x211A)
	Mode 7 settings (W)

#define	REG_M7X ((vu8)0x211F)
	Mode 7 center X (W, 2x write: low then high)

#define	REG_M7Y ((vu8)0x2120)
	Mode 7 center Y (W, 2x write: low then high)

#define	REG_MOSAIC ((vu8)0x2106)
	Mosaic effect (W)

#define	REG_MPYH ((vu8)0x2136)
	Multiplication result high (R)

#define	REG_MPYL ((vu8)0x2134)
	Multiplication result low (R)

#define	REG_MPYM ((vu8)0x2135)
	Multiplication result mid (R)

#define	REG_OAMADDH ((vu8)0x2103)
	OAM address high (W)

#define	REG_OAMADDL ((vu8)0x2102)
	OAM address low (W)

#define	REG_OAMDATA ((vu8)0x2104)
	OAM data write (W)

#define	REG_OAMDATAREAD ((vu8)0x2138)
	OAM data read (R)

#define	REG_OBJSEL ((vu8)0x2101)
	Object (sprite) size and base (W)

#define	REG_OPHCT ((vu8)0x213C)
	H counter latch (R)

#define	REG_OPVCT ((vu8)0x213D)
	V counter latch (R)

#define	REG_RDCGRAM ((vu8)0x213B)
	CGRAM data read (R)

#define	REG_RDVRAMH ((vu8)0x213A)
	VRAM data read high (R)

#define	REG_RDVRAML ((vu8)0x2139)
	VRAM data read low (R)

#define	REG_SETINI ((vu8)0x2133)
	Screen mode/video select (W)

#define	REG_SLHV ((vu8)0x2137)
	Software latch H/V counter (R)

#define	REG_STAT77 ((vu8)0x213E)
	PPU status flags (R)

#define	REG_STAT78 ((vu8)0x213F)
	PPU status flags 2 (R)

#define	REG_TM ((vu8)0x212C)
	Main screen designation (W)

#define	REG_TMW ((vu8)0x212E)
	Main screen window mask (W)

#define	REG_TS ((vu8)0x212D)
	Sub screen designation (W)

#define	REG_TSW ((vu8)0x212F)
	Sub screen window mask (W)

#define	REG_VMADDH ((vu8)0x2117)
	VRAM address high (W)

#define	REG_VMADDL ((vu8)0x2116)
	VRAM address low (W)

#define	REG_VMAIN ((vu8)0x2115)
	VRAM address increment mode (W)

#define	REG_VMDATAH ((vu8)0x2119)
	VRAM data write high (W)

#define	REG_VMDATAL ((vu8)0x2118)
	VRAM data write low (W)

#define	REG_W12SEL ((vu8)0x2123)
	BG1/BG2 window mask settings (W)

#define	REG_W34SEL ((vu8)0x2124)
	BG3/BG4 window mask settings (W)

#define	REG_WBGLOG ((vu8)0x212A)
	BG1-4 window logic (W)

#define	REG_WH0 ((vu8)0x2126)
	Window 1 left position (W)

#define	REG_WH1 ((vu8)0x2127)
	Window 1 right position (W)

#define	REG_WH2 ((vu8)0x2128)
	Window 2 left position (W)

#define	REG_WH3 ((vu8)0x2129)
	Window 2 right position (W)

#define	REG_WOBJLOG ((vu8)0x212B)
	OBJ/MATH window logic (W)

#define	REG_WOBJSEL ((vu8)0x2125)
	OBJ/MATH window mask settings (W)

Detailed Description

Picture Processing Unit registers.

Macro Definition Documentation

◆ REG_BG12NBA

#define REG_BG12NBA (*(vu8*)0x210B)

BG1/2 tile data address (W)

◆ REG_BG1HOFS

#define REG_BG1HOFS (*(vu8*)0x210D)

BG1 horizontal scroll (W, 2x write)

◆ REG_BG1SC

#define REG_BG1SC (*(vu8*)0x2107)

BG1 tilemap address (W)

◆ REG_BG1VOFS

#define REG_BG1VOFS (*(vu8*)0x210E)

BG1 vertical scroll (W, 2x write)

◆ REG_BG2HOFS

#define REG_BG2HOFS (*(vu8*)0x210F)

BG2 horizontal scroll (W, 2x write)

◆ REG_BG2SC

#define REG_BG2SC (*(vu8*)0x2108)

BG2 tilemap address (W)

◆ REG_BG2VOFS

#define REG_BG2VOFS (*(vu8*)0x2110)

BG2 vertical scroll (W, 2x write)

◆ REG_BG34NBA

#define REG_BG34NBA (*(vu8*)0x210C)

BG3/4 tile data address (W)

◆ REG_BG3HOFS

#define REG_BG3HOFS (*(vu8*)0x2111)

BG3 horizontal scroll (W, 2x write)

◆ REG_BG3SC

#define REG_BG3SC (*(vu8*)0x2109)

BG3 tilemap address (W)

◆ REG_BG3VOFS

#define REG_BG3VOFS (*(vu8*)0x2112)

BG3 vertical scroll (W, 2x write)

◆ REG_BG4HOFS

#define REG_BG4HOFS (*(vu8*)0x2113)

BG4 horizontal scroll (W, 2x write)

◆ REG_BG4SC

#define REG_BG4SC (*(vu8*)0x210A)

BG4 tilemap address (W)

◆ REG_BG4VOFS

#define REG_BG4VOFS (*(vu8*)0x2114)

BG4 vertical scroll (W, 2x write)

◆ REG_BGMODE

#define REG_BGMODE (*(vu8*)0x2105)

BG mode and tile size (W)

◆ REG_CGADD

#define REG_CGADD (*(vu8*)0x2121)

CGRAM address (W)

◆ REG_CGADSUB

#define REG_CGADSUB (*(vu8*)0x2131)

Color math control B (W)

◆ REG_CGDATA

#define REG_CGDATA (*(vu8*)0x2122)

CGRAM data write (W)

◆ REG_CGWSEL

#define REG_CGWSEL (*(vu8*)0x2130)

Color math control A (W)

◆ REG_COLDATA

#define REG_COLDATA (*(vu8*)0x2132)

Fixed color data (W)

◆ REG_INIDISP

#define REG_INIDISP (*(vu8*)0x2100)

Display control (W)

◆ REG_M7A

#define REG_M7A (*(vu8*)0x211B)

Mode 7 matrix A (W, 2x write: low then high)

◆ REG_M7B

#define REG_M7B (*(vu8*)0x211C)

Mode 7 matrix B (W, 2x write: low then high)

◆ REG_M7C

#define REG_M7C (*(vu8*)0x211D)

Mode 7 matrix C (W, 2x write: low then high)

◆ REG_M7D

#define REG_M7D (*(vu8*)0x211E)

Mode 7 matrix D (W, 2x write: low then high)

◆ REG_M7SEL

#define REG_M7SEL (*(vu8*)0x211A)

Mode 7 settings (W)

◆ REG_M7X

#define REG_M7X (*(vu8*)0x211F)

Mode 7 center X (W, 2x write: low then high)

◆ REG_M7Y

#define REG_M7Y (*(vu8*)0x2120)

Mode 7 center Y (W, 2x write: low then high)

◆ REG_MOSAIC

#define REG_MOSAIC (*(vu8*)0x2106)

Mosaic effect (W)

◆ REG_MPYH

#define REG_MPYH (*(vu8*)0x2136)

Multiplication result high (R)

◆ REG_MPYL

#define REG_MPYL (*(vu8*)0x2134)

Multiplication result low (R)

◆ REG_MPYM

#define REG_MPYM (*(vu8*)0x2135)

Multiplication result mid (R)

◆ REG_OAMADDH

#define REG_OAMADDH (*(vu8*)0x2103)

OAM address high (W)

◆ REG_OAMADDL

#define REG_OAMADDL (*(vu8*)0x2102)

OAM address low (W)

◆ REG_OAMDATA

#define REG_OAMDATA (*(vu8*)0x2104)

OAM data write (W)

◆ REG_OAMDATAREAD

#define REG_OAMDATAREAD (*(vu8*)0x2138)

OAM data read (R)

◆ REG_OBJSEL

#define REG_OBJSEL (*(vu8*)0x2101)

Object (sprite) size and base (W)

◆ REG_OPHCT

#define REG_OPHCT (*(vu8*)0x213C)

H counter latch (R)

◆ REG_OPVCT

#define REG_OPVCT (*(vu8*)0x213D)

V counter latch (R)

◆ REG_RDCGRAM

#define REG_RDCGRAM (*(vu8*)0x213B)

CGRAM data read (R)

◆ REG_RDVRAMH

#define REG_RDVRAMH (*(vu8*)0x213A)

VRAM data read high (R)

◆ REG_RDVRAML

#define REG_RDVRAML (*(vu8*)0x2139)

VRAM data read low (R)

◆ REG_SETINI

#define REG_SETINI (*(vu8*)0x2133)

Screen mode/video select (W)

◆ REG_SLHV

#define REG_SLHV (*(vu8*)0x2137)

Software latch H/V counter (R)

◆ REG_STAT77

#define REG_STAT77 (*(vu8*)0x213E)

PPU status flags (R)

◆ REG_STAT78

#define REG_STAT78 (*(vu8*)0x213F)

PPU status flags 2 (R)

◆ REG_TM

#define REG_TM (*(vu8*)0x212C)

Main screen designation (W)

◆ REG_TMW

#define REG_TMW (*(vu8*)0x212E)

Main screen window mask (W)

◆ REG_TS

#define REG_TS (*(vu8*)0x212D)

Sub screen designation (W)

◆ REG_TSW

#define REG_TSW (*(vu8*)0x212F)

Sub screen window mask (W)

◆ REG_VMADDH

#define REG_VMADDH (*(vu8*)0x2117)

VRAM address high (W)

◆ REG_VMADDL

#define REG_VMADDL (*(vu8*)0x2116)

VRAM address low (W)

◆ REG_VMAIN

#define REG_VMAIN (*(vu8*)0x2115)

VRAM address increment mode (W)

◆ REG_VMDATAH

#define REG_VMDATAH (*(vu8*)0x2119)

VRAM data write high (W)

◆ REG_VMDATAL

#define REG_VMDATAL (*(vu8*)0x2118)

VRAM data write low (W)

◆ REG_W12SEL

#define REG_W12SEL (*(vu8*)0x2123)

BG1/BG2 window mask settings (W)

◆ REG_W34SEL

#define REG_W34SEL (*(vu8*)0x2124)

BG3/BG4 window mask settings (W)

◆ REG_WBGLOG

#define REG_WBGLOG (*(vu8*)0x212A)

BG1-4 window logic (W)

◆ REG_WH0

#define REG_WH0 (*(vu8*)0x2126)

Window 1 left position (W)

◆ REG_WH1

#define REG_WH1 (*(vu8*)0x2127)

Window 1 right position (W)

◆ REG_WH2

#define REG_WH2 (*(vu8*)0x2128)

Window 2 left position (W)

◆ REG_WH3

#define REG_WH3 (*(vu8*)0x2129)

Window 2 right position (W)

◆ REG_WOBJLOG

#define REG_WOBJLOG (*(vu8*)0x212B)

OBJ/MATH window logic (W)

◆ REG_WOBJSEL

#define REG_WOBJSEL (*(vu8*)0x2125)

OBJ/MATH window mask settings (W)

Macros