registers.h

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#ifndef OPENSNES_REGISTERS_H
#define OPENSNES_REGISTERS_H
 
#include <snes/types.h>
 
/*============================================================================
 * PPU Registers ($2100-$213F)
 *============================================================================*/


#define REG_INIDISP     (*(vu8*)0x2100)

#define REG_OBJSEL      (*(vu8*)0x2101)

#define REG_OAMADDL     (*(vu8*)0x2102)

#define REG_OAMADDH     (*(vu8*)0x2103)

#define REG_OAMDATA     (*(vu8*)0x2104)

#define REG_BGMODE      (*(vu8*)0x2105)

#define REG_MOSAIC      (*(vu8*)0x2106)

#define REG_BG1SC       (*(vu8*)0x2107)

#define REG_BG2SC       (*(vu8*)0x2108)

#define REG_BG3SC       (*(vu8*)0x2109)

#define REG_BG4SC       (*(vu8*)0x210A)

#define REG_BG12NBA     (*(vu8*)0x210B)

#define REG_BG34NBA     (*(vu8*)0x210C)

#define REG_BG1HOFS     (*(vu8*)0x210D)

#define REG_BG1VOFS     (*(vu8*)0x210E)

#define REG_BG2HOFS     (*(vu8*)0x210F)

#define REG_BG2VOFS     (*(vu8*)0x2110)

#define REG_BG3HOFS     (*(vu8*)0x2111)

#define REG_BG3VOFS     (*(vu8*)0x2112)

#define REG_BG4HOFS     (*(vu8*)0x2113)

#define REG_BG4VOFS     (*(vu8*)0x2114)

#define REG_VMAIN       (*(vu8*)0x2115)
#define VMAIN_INC1      0x80
#define VMAIN_INC32     0x81

#define REG_VMADDL      (*(vu8*)0x2116)

#define REG_VMADDH      (*(vu8*)0x2117)

#define REG_VMDATAL     (*(vu8*)0x2118)

#define REG_VMDATAH     (*(vu8*)0x2119)

#define REG_M7SEL       (*(vu8*)0x211A)

#define REG_M7A         (*(vu8*)0x211B)

#define REG_M7B         (*(vu8*)0x211C)

#define REG_M7C         (*(vu8*)0x211D)

#define REG_M7D         (*(vu8*)0x211E)

#define REG_M7X         (*(vu8*)0x211F)

#define REG_M7Y         (*(vu8*)0x2120)

#define REG_CGADD       (*(vu8*)0x2121)

#define REG_CGDATA      (*(vu8*)0x2122)

#define REG_W12SEL      (*(vu8*)0x2123)

#define REG_W34SEL      (*(vu8*)0x2124)

#define REG_WOBJSEL     (*(vu8*)0x2125)

#define REG_WH0         (*(vu8*)0x2126)

#define REG_WH1         (*(vu8*)0x2127)

#define REG_WH2         (*(vu8*)0x2128)

#define REG_WH3         (*(vu8*)0x2129)

#define REG_WBGLOG      (*(vu8*)0x212A)

#define REG_WOBJLOG     (*(vu8*)0x212B)

#define REG_TM          (*(vu8*)0x212C)

#define REG_TS          (*(vu8*)0x212D)

#define REG_TMW         (*(vu8*)0x212E)

#define REG_TSW         (*(vu8*)0x212F)

#define REG_CGWSEL      (*(vu8*)0x2130)

#define REG_CGADSUB     (*(vu8*)0x2131)

#define REG_COLDATA     (*(vu8*)0x2132)

#define REG_SETINI      (*(vu8*)0x2133)

#define REG_MPYL        (*(vu8*)0x2134)

#define REG_MPYM        (*(vu8*)0x2135)

#define REG_MPYH        (*(vu8*)0x2136)

#define REG_SLHV        (*(vu8*)0x2137)

#define REG_OAMDATAREAD (*(vu8*)0x2138)

#define REG_RDVRAML     (*(vu8*)0x2139)

#define REG_RDVRAMH     (*(vu8*)0x213A)

#define REG_RDCGRAM     (*(vu8*)0x213B)

#define REG_OPHCT       (*(vu8*)0x213C)

#define REG_OPVCT       (*(vu8*)0x213D)

#define REG_STAT77      (*(vu8*)0x213E)

#define REG_STAT78      (*(vu8*)0x213F)
 /* end of ppu_regs */
 
/*============================================================================
 * CPU Registers ($4200-$421F)
 *============================================================================*/


#define REG_NMITIMEN    (*(vu8*)0x4200)

#define REG_WRIO        (*(vu8*)0x4201)

#define REG_WRMPYA      (*(vu8*)0x4202)

#define REG_WRMPYB      (*(vu8*)0x4203)

#define REG_WRDIVL      (*(vu8*)0x4204)

#define REG_WRDIVH      (*(vu8*)0x4205)

#define REG_WRDIVB      (*(vu8*)0x4206)

#define REG_HTIMEL      (*(vu8*)0x4207)

#define REG_HTIMEH      (*(vu8*)0x4208)

#define REG_VTIMEL      (*(vu8*)0x4209)

#define REG_VTIMEH      (*(vu8*)0x420A)

#define REG_MDMAEN      (*(vu8*)0x420B)

#define REG_HDMAEN      (*(vu8*)0x420C)

#define REG_MEMSEL      (*(vu8*)0x420D)

#define REG_RDNMI       (*(vu8*)0x4210)

#define REG_TIMEUP      (*(vu8*)0x4211)

#define REG_HVBJOY      (*(vu8*)0x4212)

#define REG_RDIO        (*(vu8*)0x4213)

#define REG_RDDIVL      (*(vu8*)0x4214)

#define REG_RDDIVH      (*(vu8*)0x4215)

#define REG_RDMPYL      (*(vu8*)0x4216)

#define REG_RDMPYH      (*(vu8*)0x4217)

#define REG_JOYA        (*(vu8*)0x4016)

#define REG_JOYB        (*(vu8*)0x4017)

#define REG_JOY1L       (*(vu8*)0x4218)

#define REG_JOY1H       (*(vu8*)0x4219)

#define REG_JOY2L       (*(vu8*)0x421A)

#define REG_JOY2H       (*(vu8*)0x421B)

#define REG_JOY3L       (*(vu8*)0x421C)

#define REG_JOY3H       (*(vu8*)0x421D)

#define REG_JOY4L       (*(vu8*)0x421E)

#define REG_JOY4H       (*(vu8*)0x421F)
 /* end of cpu_regs */
 
/*============================================================================
 * DMA Registers ($43x0-$43xF)
 *============================================================================*/


#define REG_DMAP(n)     (*(vu8*)(0x4300 + ((n) << 4)))

#define REG_BBAD(n)     (*(vu8*)(0x4301 + ((n) << 4)))

#define REG_A1TL(n)     (*(vu8*)(0x4302 + ((n) << 4)))

#define REG_A1TH(n)     (*(vu8*)(0x4303 + ((n) << 4)))

#define REG_A1B(n)      (*(vu8*)(0x4304 + ((n) << 4)))

#define REG_DASL(n)     (*(vu8*)(0x4305 + ((n) << 4)))

#define REG_DASH(n)     (*(vu8*)(0x4306 + ((n) << 4)))
 /* end of dma_regs */
 
/*============================================================================
 * APU Registers ($2140-$2143)
 *============================================================================*/


#define REG_APUIO0      (*(vu8*)0x2140)

#define REG_APUIO1      (*(vu8*)0x2141)

#define REG_APUIO2      (*(vu8*)0x2142)

#define REG_APUIO3      (*(vu8*)0x2143)
 /* end of apu_regs */
 
/*============================================================================
 * Register Value Constants
 *============================================================================*/

 
/* INIDISP values */
#define INIDISP_FORCE_BLANK  0x80  
#define INIDISP_BRIGHTNESS(n) ((n) & 0x0F)  
 
/* BGMODE values */
#define BGMODE_MODE0  0  
#define BGMODE_MODE1  1  
#define BGMODE_MODE2  2  
#define BGMODE_MODE3  3  
#define BGMODE_MODE7  7  
 
/* NMITIMEN values */
#define NMITIMEN_NMI_ENABLE   0x80  
#define NMITIMEN_JOY_ENABLE   0x01  
 
/* TM/TS values (main/sub screen enable) */
#define TM_BG1  BIT(0)  
#define TM_BG2  BIT(1)  
#define TM_BG3  BIT(2)  
#define TM_BG4  BIT(3)  
#define TM_OBJ  BIT(4)  
 /* end of reg_const */
 
#endif /* OPENSNES_REGISTERS_H */