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registers.h
Go to the documentation of this file.
1
33#ifndef OPENSNES_REGISTERS_H
34#define OPENSNES_REGISTERS_H
35
36#include <snes/types.h>
37
38/*============================================================================
39 * PPU Registers ($2100-$213F)
40 *============================================================================*/
41
49#define REG_INIDISP (*(vu8*)0x2100)
50
52#define REG_OBJSEL (*(vu8*)0x2101)
53
55#define REG_OAMADDL (*(vu8*)0x2102)
56
58#define REG_OAMADDH (*(vu8*)0x2103)
59
61#define REG_OAMDATA (*(vu8*)0x2104)
62
64#define REG_BGMODE (*(vu8*)0x2105)
65
67#define REG_MOSAIC (*(vu8*)0x2106)
68
70#define REG_BG1SC (*(vu8*)0x2107)
71
73#define REG_BG2SC (*(vu8*)0x2108)
74
76#define REG_BG3SC (*(vu8*)0x2109)
77
79#define REG_BG4SC (*(vu8*)0x210A)
80
82#define REG_BG12NBA (*(vu8*)0x210B)
83
85#define REG_BG34NBA (*(vu8*)0x210C)
86
88#define REG_BG1HOFS (*(vu8*)0x210D)
89
91#define REG_BG1VOFS (*(vu8*)0x210E)
92
94#define REG_BG2HOFS (*(vu8*)0x210F)
95
97#define REG_BG2VOFS (*(vu8*)0x2110)
98
100#define REG_BG3HOFS (*(vu8*)0x2111)
101
103#define REG_BG3VOFS (*(vu8*)0x2112)
104
106#define REG_BG4HOFS (*(vu8*)0x2113)
107
109#define REG_BG4VOFS (*(vu8*)0x2114)
110
112#define REG_VMAIN (*(vu8*)0x2115)
113
115#define REG_VMADDL (*(vu8*)0x2116)
116
118#define REG_VMADDH (*(vu8*)0x2117)
119
121#define REG_VMDATAL (*(vu8*)0x2118)
122
124#define REG_VMDATAH (*(vu8*)0x2119)
125
127#define REG_M7SEL (*(vu8*)0x211A)
128
130#define REG_M7A (*(vu8*)0x211B)
131
133#define REG_M7B (*(vu8*)0x211C)
134
136#define REG_M7C (*(vu8*)0x211D)
137
139#define REG_M7D (*(vu8*)0x211E)
140
142#define REG_M7X (*(vu8*)0x211F)
143
145#define REG_M7Y (*(vu8*)0x2120)
146
148#define REG_CGADD (*(vu8*)0x2121)
149
151#define REG_CGDATA (*(vu8*)0x2122)
152
154#define REG_W12SEL (*(vu8*)0x2123)
155
157#define REG_W34SEL (*(vu8*)0x2124)
158
160#define REG_WOBJSEL (*(vu8*)0x2125)
161
163#define REG_WH0 (*(vu8*)0x2126)
164
166#define REG_WH1 (*(vu8*)0x2127)
167
169#define REG_WH2 (*(vu8*)0x2128)
170
172#define REG_WH3 (*(vu8*)0x2129)
173
175#define REG_WBGLOG (*(vu8*)0x212A)
176
178#define REG_WOBJLOG (*(vu8*)0x212B)
179
181#define REG_TM (*(vu8*)0x212C)
182
184#define REG_TS (*(vu8*)0x212D)
185
187#define REG_TMW (*(vu8*)0x212E)
188
190#define REG_TSW (*(vu8*)0x212F)
191
193#define REG_CGWSEL (*(vu8*)0x2130)
194
196#define REG_CGADSUB (*(vu8*)0x2131)
197
199#define REG_COLDATA (*(vu8*)0x2132)
200
202#define REG_SETINI (*(vu8*)0x2133)
203
205#define REG_MPYL (*(vu8*)0x2134)
206
208#define REG_MPYM (*(vu8*)0x2135)
209
211#define REG_MPYH (*(vu8*)0x2136)
212
214#define REG_SLHV (*(vu8*)0x2137)
215
217#define REG_OAMDATAREAD (*(vu8*)0x2138)
218
220#define REG_RDVRAML (*(vu8*)0x2139)
221
223#define REG_RDVRAMH (*(vu8*)0x213A)
224
226#define REG_RDCGRAM (*(vu8*)0x213B)
227
229#define REG_OPHCT (*(vu8*)0x213C)
230
232#define REG_OPVCT (*(vu8*)0x213D)
233
235#define REG_STAT77 (*(vu8*)0x213E)
236
238#define REG_STAT78 (*(vu8*)0x213F)
239
/* end of ppu_regs */
241
242/*============================================================================
243 * CPU Registers ($4200-$421F)
244 *============================================================================*/
245
253#define REG_NMITIMEN (*(vu8*)0x4200)
254
256#define REG_WRIO (*(vu8*)0x4201)
257
259#define REG_WRMPYA (*(vu8*)0x4202)
260
262#define REG_WRMPYB (*(vu8*)0x4203)
263
265#define REG_WRDIVL (*(vu8*)0x4204)
266
268#define REG_WRDIVH (*(vu8*)0x4205)
269
271#define REG_WRDIVB (*(vu8*)0x4206)
272
274#define REG_HTIMEL (*(vu8*)0x4207)
275
277#define REG_HTIMEH (*(vu8*)0x4208)
278
280#define REG_VTIMEL (*(vu8*)0x4209)
281
283#define REG_VTIMEH (*(vu8*)0x420A)
284
286#define REG_MDMAEN (*(vu8*)0x420B)
287
289#define REG_HDMAEN (*(vu8*)0x420C)
290
292#define REG_MEMSEL (*(vu8*)0x420D)
293
295#define REG_RDNMI (*(vu8*)0x4210)
296
298#define REG_TIMEUP (*(vu8*)0x4211)
299
301#define REG_HVBJOY (*(vu8*)0x4212)
302
304#define REG_RDIO (*(vu8*)0x4213)
305
307#define REG_RDDIVL (*(vu8*)0x4214)
308
310#define REG_RDDIVH (*(vu8*)0x4215)
311
313#define REG_RDMPYL (*(vu8*)0x4216)
314
316#define REG_RDMPYH (*(vu8*)0x4217)
317
319#define REG_JOYA (*(vu8*)0x4016)
320
322#define REG_JOYB (*(vu8*)0x4017)
323
325#define REG_JOY1L (*(vu8*)0x4218)
326
328#define REG_JOY1H (*(vu8*)0x4219)
329
331#define REG_JOY2L (*(vu8*)0x421A)
332
334#define REG_JOY2H (*(vu8*)0x421B)
335
337#define REG_JOY3L (*(vu8*)0x421C)
338
340#define REG_JOY3H (*(vu8*)0x421D)
341
343#define REG_JOY4L (*(vu8*)0x421E)
344
346#define REG_JOY4H (*(vu8*)0x421F)
347
/* end of cpu_regs */
349
350/*============================================================================
351 * DMA Registers ($43x0-$43xF)
352 *============================================================================*/
353
361#define REG_DMAP(n) (*(vu8*)(0x4300 + ((n) << 4)))
362
364#define REG_BBAD(n) (*(vu8*)(0x4301 + ((n) << 4)))
365
367#define REG_A1TL(n) (*(vu8*)(0x4302 + ((n) << 4)))
368
370#define REG_A1TH(n) (*(vu8*)(0x4303 + ((n) << 4)))
371
373#define REG_A1B(n) (*(vu8*)(0x4304 + ((n) << 4)))
374
376#define REG_DASL(n) (*(vu8*)(0x4305 + ((n) << 4)))
377
379#define REG_DASH(n) (*(vu8*)(0x4306 + ((n) << 4)))
380
/* end of dma_regs */
382
383/*============================================================================
384 * APU Registers ($2140-$2143)
385 *============================================================================*/
386
400#define REG_APUIO0 (*(vu8*)0x2140)
401
403#define REG_APUIO1 (*(vu8*)0x2141)
404
406#define REG_APUIO2 (*(vu8*)0x2142)
407
409#define REG_APUIO3 (*(vu8*)0x2143)
410
/* end of apu_regs */
412
413/*============================================================================
414 * Register Value Constants
415 *============================================================================*/
416
423/* INIDISP values */
424#define INIDISP_FORCE_BLANK 0x80
425#define INIDISP_BRIGHTNESS(n) ((n) & 0x0F)
427/* BGMODE values */
428#define BGMODE_MODE0 0
429#define BGMODE_MODE1 1
430#define BGMODE_MODE2 2
431#define BGMODE_MODE3 3
432#define BGMODE_MODE7 7
434/* NMITIMEN values */
435#define NMITIMEN_NMI_ENABLE 0x80
436#define NMITIMEN_JOY_ENABLE 0x01
438/* TM/TS values (main/sub screen enable) */
439#define TM_BG1 BIT(0)
440#define TM_BG2 BIT(1)
441#define TM_BG3 BIT(2)
442#define TM_BG4 BIT(3)
443#define TM_OBJ BIT(4)
/* end of reg_const */
446
447#endif /* OPENSNES_REGISTERS_H */
types.h
OpenSNES Standard Types.